To manufacture a semiconductor device, an electronic circuit is chemically and physically integrated into a substrate such as a silicon wafer by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be conductive for conductor and resistor fabrication and can also be of differing conductivity types, which is essential for transistor and diode fabrication. Degrees of resistance, capacitance, or conductivity are controllable, as are the physical dimensions and locations of the patterned regions and layers, making circuit integration possible.
In this disclosure, "n-type" denotes silicon that has been doped with atoms having more than four valence electrons (group V or higher), such as arsenic or phosphorus, which introduce negatively charged majority carriers into the silicon, and "p-type" denotes silicon doped with atoms having less than four valence electrons (group III or lower), such as boron, which introduce positively charged majority carriers. The majority charge carrier type is also referred to as conductivity type. "Poly" denotes polycyrstalline silicon. "Poly 1" denotes a first poly layer but does not imply a second poly layer, and "Poly 2" denotes a second poly layer. By photomasking, geometries on the order of a micron or less are obtainable for device elements in the IC.
In the manufacture of semiconductors, several process steps are required to produce a functional die. A wafer of a starting material such as silicon or gallium arsenide is layered with oxide, poly, nitride, photoresist, and other materials in various configurations, depending on the type and design of the device which is being produced. Each step may require the local deposition, growth, or other formation of one of the above listed materials (patterning), or a blanket layer of the material may be laid down and a pattern etched away with chemicals or abraded away by particles.
During the fabrication of semiconductor devices using metal oxide semiconductor (MOS) technology, conductive interconnects (or contacts) between different layers or types of conductive material are required to form a circuit. For example, as a MOS transistor is formed in a silicon substrate's active area, its gate, formed from a first poly layer, has to be connected to other circuitry by a conductor, such as a second layer of poly.
Contacts between layers can comprise two types. In this disclosure, non self-aligned contacts refer to contacts formed by a process which has little or no tolerance for misalignment of masks, especially if the alignment cannot extend beyond the poly structure to which the mask is being aligned. If the mask is misaligned to a point that it extends beyond the edge of the poly structure, an etch or deposition of a material such as photoresist with the misaligned mask produces a device which does not function properly. A self-aligned process refers to a process which has a high tolerance for misalignment of a mask, especially if the mask can be aligned completely off the poly structure to which the mask is being aligned.
Many current methods of forming a contact between two conductive layers such as poly requires expanded dimensions of the poly 1 layer in the area of the contact. FIG. 1 is a top view of the poly 1 layer which shows a poly 1 line 10 with expanded dimensions 12. A first layer of poly 10 has been formed on the surface of the substrate (not shown), then a layer of insulator such as oxide (not shown) is formed on the first poly layer 10. An etch through a specific area 14 of the oxide allows a second layer of poly (not shown) formed thereon to contact the first poly layer 10. The expanded dimensions 12 of the bottom poly layer 10 allows for misalignment of the etch 14 through the oxide layer. Misalignment of the etch can result from misalignment of the photomask during the etch step. This is an example of a nonaligned process, because the edge of the mask cannot extend beyond the boundary of the poly 1 line without etching down into the substrate. After a misaligned etch, a poly 2 layer deposited over the etch into the substrate would allow the poly 2 layer to contact the substrate.
This method of forming a contact requires a greater amount of substrate surface space due to the increased size 12 of the poly 1 layer 10 in the contact area 14, thereby increasing the size of the device as many of these structures can be formed on the wafer surface. In cases where the etch mask is greatly misaligned, the etch can expose the substrate which can allow the poly 2 layer to make contact with the substrate, and may thereby produce a defective device.
A typical self-aligned process for forming poly 1 to poly 2 contacts to a MOS transistor is shown in the cross sections of FIGS. 2a-2c. As shown in FIG. 2a, a wafer substrate 20 is processed to have field oxide 22, gate oxide 24, a first layer of poly (poly 1) 26, and a patterned layer of photoresist 28. An etch patterns the poly 1 layer 26 to form a transistor gate 30 as shown in FIG. 2b. Next, oxide spacers 32 are formed to offset the transistor source 34 and drain 36 regions of the MOS device from the gate/channel region, and to protect the gate oxide 24 under the spacers 32 during later etching steps. An implant forms source 34 and drain 36 wells in the substrate 20. A method of implanting the source 34 and drain 36 regions is to perform a light implant before the spacers 32 are formed, and a heavier implant after the spacers 32 are formed, thus resulting in a double scalloped well as shown. This implantation method is known in the art, and is not critical to the invention. Other implant methods are known in the art and would work when used if the inventive process for contact formation is used. Another layer of oxide 38 is formed, and a second layer photoresist 40 is patterned over the oxide layer 38. The oxide 38 is etched away to selectively expose the poly 1 layer 26, which also removes material from the oxide spacers 32. The spacers 32 thereby prevent an etch through the gate oxide 24 which would allow the poly 2 layer 42 to contact the substrate 20. Finally, as shown in FIG. 2c, a second layer of poly (poly 2) 42 is patterned, thereby forming contacts at 44 between poly 1 26 and poly 2 42. This process is self-aligned because the photomask to deposit the photoresist can be misaligned over the edge of the poly 1 layer 26 to a degree equal to the width of the spacers 32. As long as the mask is misaligned no more than the width of the spacers 32, the oxide etch will not erode the gate oxide 24 to expose the substrate 20.
Other problems in addition to the possibility of photomask misalignment and increased poly 1 size described above also exist with this type of self-aligned process. For example, the oxide layer 38 formed over the poly 1 26 layer must have a controlled thickness. If the oxide 38 is too thick, then to remove the oxide over the poly 1 layer in the contact area requires such a long etch that the oxide spacers 32 are also etched away, which allows the gate oxide 24 to be etched through, which exposes the substrate 20. The subsequent poly 2 layer 42 would then make contact with the substrate 20, thereby producing a defective device. This process therefore requires larger spacers 32 than would normally be used in simple MOS devices. Typical MOS spacers may not be as large as the worst case misalignment, and this process would therefore require additional processing to build up the spacers.
A process which allows for self-alignment of the contacts independent of the spacer width would solve the problems associated with previous methods of contact formation.